1. Field of the Invention
The present invention relates to a gate insulating structure for power devices, and to a related manufacturing process.
2. Discussion of the Related Art
In power MOS devices, the gate insulation in respect to the metal source layer is assured by a dielectric layer that covers the polysilicon constituting the gate, insulating it from the metal source layer. This occurs through a deposition of a deposited oxide layer (vapox) or of a phosphorus doped deposited oxide (pvapox), and a subsequent photolithographic process that defines the contact between the source and the body.
FIG. 1 shows a cross-sectional view of a basic structure of a power MOS device, having a gate insulation according to the prior art. A dielectric layer 6 formed by deposited oxide (vapox) or by phosphorus doped deposited oxide (pvapox) assures the insulation of the polysilicon layer 5, corresponding to the gate electrode, from the metal layer 7 (constituted, for example, by aluminum), both over the upper surface and over the vertical walls. The metal layer 7 connects the source regions 3 and the body region 2, obtained in the semiconductor layer 1. A thin gate oxide layer 4 is located under the polysilicon layer 5.
The polysilicon layer 5 vertical wall is protected by the dielectric thickness which depends on the process conditions and on the utilized photoexposure machines. Generally, this means that the distance between contact and polysilicon can not be reduced under one micron (usually such a distance is between 1 and 3 xcexcm). The problems related to this technique come out in the case where the dimensions of the polysilicon opening are about one micron, because the contact opening and the lateral insulation of the vertical polysilicon layer wall must be assured simultaneously.
In order to solve the above mentioned problems, other techniques for obtaining gate insulation and contact opening have been introduced. These techniques use a process of spacer formation in order to obtain, at the same time, the gate insulation and the contact opening, without using photolithographic techniques. An example of such a manufacturing technique for the spacer formation is provided by U.S. Pat. No. 4,256,514 in the name of IBM.
FIG. 2 shows a basic structure of a power MOS device wherein spacers 8 are utilized for lateral insulation of the polysilicon layer 5 walls. In this case the dimensions of the spacer 8 xe2x80x9cfootxe2x80x9d depend on the height of the superimposed layers structure constituted by the gate oxide layer 4 (having a thickness comprised between 100 and 500 xc3x85), by the polysilicon layer 5 and by the vapox layer 6 both with a thickness comprised between 2000 and 5000 xc3x85, and are comprised between 1000 and 4000 xc3x85 and then submicrometric: such a feature allows obtaining polysilicon openings of about one micron or less, and contacts lower than one micron.
The spacer as described has been commonly used in VLSI technology as a technique for obtaining alignment of implants with submicrometric dimensions otherwise impossible through photolithographic techniques.
Other gate insulation techniques provide for spacers constituted by silicon nitride. The silicon nitride represents an ideal material for obtaining a gate insulation along the vertical walls, due to its physic-chemical properties (a very good insulator for diffusion of water, humidity, sodium and oxygen) and to its capability of being deposited with a very good coverage.
The utilization of silicon nitride for obtaining spacers offers excellent results in terms of gate insulation, but produces serious problems with respect to good device operation due to the stress that the nitride transmits to the silicon. The stress transmitted by the nitride to the silicon (highly depending on the deposited nitride thickness) produces some dislocations in the regions under the spacers, which dislocations increase the device leakage current, and moreover these dislocations propagate in the channel regions and in the regions under the gate oxide, degrading the oxide quality.
The stress transmitted by the silicon nitride spacer that can generate and propagate dislocations or fractures, can be caused by the different thermal expansion coefficients between silicon and nitride film. Furthermore, the nitride transmits compression or tension stress to the silicon according to the deposition temperature, so causing the generation of dislocations or fractures in the silicon into contact.
A solution of the above mentioned problems about stress and subsequent dislocations in the silicon is provided by the substitution of the silicon nitride with a deposited oxide (vapox) or a phosphorus doped deposited oxide (pvapox) for the insulating spacer formation.
Such materials have problems related to the submicrometric spacer dimensions, even if they do not produce stress in the silicon structure and then undesirable dislocations in it. By subjecting the power MOS devices comprising vapox or pvapox spacers to a reliability test called a xe2x80x9cpressure-cookerxe2x80x9d test, which consists of keeping the device at an ambient temperature of 175xc2x0 C. with 80% humidity for a complete time between 168 and 336 hours, a fall in threshold voltage of between 10% and 50% of the initial value is obtained. Moreover, as a result of the above mentioned phenomenon, the following features occur:
by applying a positive voltage between the gate electrode and the drain electrode, a threshold voltage recovery is obtained;
by applying a negative voltage between the gate electrode and the drain electrode, a further fall in threshold voltage is obtained;
the above mentioned variations are strongly affected by temperature (in a range between 25xc2x0 C. and 200xc2x0 C., the time changes from many hours to a few minutes).
To explain such a mechanism, an implication of the reaction between the metal (for example aluminum) layer and water during the time the device is in the humid, high temperature environment, is supposed: such a reaction produces protons (hydrogen ions) which cross the spacer (if sufficiently thin) and reach the silicon wherein they can bind themselves to the ion of the material constituting the body (for example boron) in the channel region, so producing a fall in channel charge concentration and a consequent fall in threshold voltage. It is evident that such a mechanism particularly depends on the submicrometric dimensions of the spacer used for the gate insulation.
As described till now, it appears that when the dimensions of the insulating layer of the vertical gate wall are submicrometric, the utilization of conventional materials like vapox or pvapox to obtain insulating spacers produces problems related to the threshold voltage; on the other hand, the utilization of alternative materials like silicon nitride generates problems related to the stress transmission that can cause dislocations or fractures in the silicon.
In view of the state of the art described, it is an object of the present invention to provide a gate insulation structure for power devices, in order to solve at least the above-mentioned problems.
According to the present invention, this and other objects are achieved by a semiconductor power device comprising a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity comprising source regions of the first type of conductivity is formed, a gate oxide layer superimposed to said semiconductor layer with an opening over said body region, polysilicon regions superimposed to said gate oxide layer, regions of a first insulating material superimposed to said polysilicon regions, comprising regions of a second insulating material situated on a side of both said polysilicon regions and said regions of a first insulating material and over zones of said gate oxide layer situated near said opening on said body region, oxide regions interposed between said polysilicon regions and said regions of a second insulating material, oxide spacers superimposed to said regions of a second insulating material.